Static memory cell having independent data holding voltage

ABSTRACT

A static memory cell, composed of cross-coupled MOS transistors having a relatively high threshold voltage, is equipped with MOS transistors for controlling the power supply line voltage of the memory cell. To permit the voltage difference between two data storage nodes in the inactivated memory cell to exceed the voltage difference between the two nodes when write data is applied from a data line pair DL and /DL to the two nodes in the activated memory cell, the power supply line voltage control transistors are turned on to apply a high voltage VCH to the power supply lines after the word line voltage is turned off. The data holding voltage in the memory cell can be activated to a high voltage independent of the data line voltage, and the data holding voltage can be dynamically set so that read and write operations can be performed at high speed with low power consumption.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor integratedcircuit that is operated at a low voltage and which employs a staticmemory cell composed of MIS (metal insulator semiconductor) or MOS(metal oxide semiconductor) transistors (hereafter, “MOS transistors”).More particularly, the present invention relates to a circuit suited fora high-speed/low-power static memory, such as SRAM (static random accessmemory).

[0003] A gate-insulated field-effect transistor, such as a MOStransistor, requires an operating voltage that decreases as thetransistor size decreases, because the breakdown voltage of thetransistor decreases with the smaller size. As well, the thresholdvoltage (VT) of the MOS transistor must be lowered in accordance withthe drop of operating voltage so as to retain high-speed operation,because the operating speed is dominated by the effective gate voltageof the MOS transistor (i.e., the operating voltage minus VT), andincreases as the difference increases.

[0004] Generally speaking, however, if the VT is lower than about 0.4 V,a direct subthreshold current, which exponentially increases with thedrop in VT, will flow through the MOS transistor which shouldintrinsically be cut off. As a result, the direct current greatlyincreases in a semiconductor integrated circuit composed of a number ofMOS transistors, even if the circuit is a CMOS circuit. Hence, thedirect current is a significant problem for future semiconductorintegrated circuit design, in which high speed, low power consumption,and low voltage operation are important. Specifically, the subthresholdcurrents accumulate to establish the large direct current in the entirechip. Thus, the VT of the cross-coupled transistors of the static memorycells cannot be reduced below about 0.4 V. Therefore, the effective gatevoltage can only decrease as the operating voltage decreases. As aresult, the margin of the memory cells is narrowed or the operatingspeed is lowered, becoming more susceptible to influences of VTvariation during fabrication, caused by dispersion.

[0005]FIG. 2 shows a memory cell for illustrating the problems of theprior art, and a waveform timing chart for explaining these problems inmore detail.

[0006] The memory cell of FIG. 2 is exemplified by a CMOS-type staticmemory (SRAM). The memory cell is said to be “inactivated” when data arestored such that a word line (WL) is at a low level of 0 V, a datastorage node N2 in the cell is at a high level equal to the supplyvoltage VCC of 1 V, and another data storage node N1 is at a low levelof 0 V. In the prior art, the threshold voltage VT of all transistors ofthe memory cell is greater than 0.4 V so that both an N-channel MOStransistor QS2 and a P-channel MOS transistor QC1 are off, because thevoltage between the gates and sources of QS2 and QC1 is 0 V. The currentflowing through the VCC terminal can thus be neglected, which is why theSRAM is considered to be “low power”.

[0007] The voltage margin of this memory cell becomes smaller as thedifference (VCC−VT) becomes smaller. Thus, the VT must be decreased fora lower VCC. As the VT is lowered below 0.4 V, however, the subthresholdcurrent flows through transistors QS2 and QC2, which should beintrinsically off, and so the subthreshold current exponentiallyincreases as VT decreases. Generally speaking, the VT will disperse withthe fluctuation of the fabrication process, and the subthreshold currentwill increase for higher temperatures. This current will furtherincrease if both the VT dispersion and junction temperature increase areconsidered.

[0008] Moreover, since the subthreshold current flows through all of thememory cells in the chip, a total current as high as 10 mA or larger mayflow through an SRAM of, for example, about 128 Kbits. This current isalso the data holding current for the entire cell array. This is aserious problem, considering that the data holding current of theordinary SRAM using MOS transistors having a relatively high thresholdvoltage so as to suppress the subthreshold current substantially can bemade less than 10 μA. To prevent this high aggregate current, therefore,the VT has been set at a relatively high level of 0.4 V or higher.

[0009] Some consideration is also given to lowering the VCC, with the VTfixed at 0.5 V, for example. The demand for dropping the VCC comes notonly from the low breakdown voltage of the MOS transistors, but alsofrom low power consumption, or drive by a single battery. If theminiaturization of MOS transistors advances so that the channel lengthis less than 0.5 μm, or that the gate insulator has a thickness of lessthan 6 nm, the transistor can operate at a sufficiently high speed evenwith an external supply voltage VCC as low as 1.5 to 1.0 V. Thus, thevoltage VCC can be lowered to that extent, with preference given tolower power consumption.

[0010] Dropping the VCC, however, decreases seriously the voltage marginof the memory cell, because the effective gate voltage of the conductingtransistor QS1 is “VCC−VT”, so that the effective gate voltage becomessmaller as the VCC comes closer to VT. This drastically increases thefluctuation ratio of the VT to the dispersion. Moreover, theconventional protection against soft errors will drop together with themargin of the threshold voltage difference (offset voltage) between thecross-coupled paired transistors (QS1 and QS2, QC1 and QC2) in thememory cell to the equivalent noise.

[0011] When the memory cell is “activated”, speed or operation margin isalso reduced if the VT is as high as 0.5 V, with a low VCC. If a VCC of1 V, for example, is applied to the word line WL, transistors QT1 andQS1 are turned on, so that a small voltage change of 0.2 V is caused bythe current flowing through the transistors and the load resistor(composed of MOS transistors) connected to a data line DL. On the otherhand, transistor QS2 has a gate voltage that is far lower than the VTand is off, so that no voltage change appears in the other data line/DL. By the voltage polarity of this data line pair,-the stored data ofthe memory cell are discriminated and read out. This discrimination ismore stable for a larger change in the voltage appearing on the dataline DL. Such a large voltage change requires a high and constantcurrent to flow through QS1 and QT1. However, this current becomes loweras the VCC drops because QS1 and QT1 have substantially equal effectivegate voltages of (VCC−VT), and is seriously influenced by the dispersionof the VT.

[0012] As described above, the circuit and drive system of the prior artsuffers from an extreme increase of the direct current, adrop/fluctuation of operating speed, or a drop in operation margin, asthe VCC drops. As a result, the performance of the SRAM chip ormicroprocessor chip containing an SRAM is seriously deteriorated as theVCC drops.

SUMMARY OF THE INVENTION

[0013] An object of the present invention is to suppress the increase inthe subthreshold current and the drop of the voltage margin caused bythe low voltage operation of the cross-coupled MOS transistor staticmemory cell, in a static memory or semiconductor integrated circuit inwhich the static memory is incorporated.

[0014] This object can be realized by controlling the voltage of atleast one power supply line of a static memory cell having cross-coupledMOS transistors which conduct no substantial current between theirdrains and sources, even if the gate and source voltages are equal. Thevoltage difference between the two data storage nodes in the inactivatedmemory cell may exceed the voltage difference between the two datastorage nodes of the cell when a voltage corresponding to write data isapplied from the data line pair to the data storage nodes of the memorycell when activated. As a result, the voltage between the two datastorage nodes in the memory cell can be made sufficiently high even ifthe main supply voltage is low when the memory cell is activated, sothat the memory cell can be stably operated with low power consumptionand a wide operation margin.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIGS. 1(a)-1(c) illustrate features of the present invention forcontrolling the power supply line voltage of a static memory cell;

[0016]FIG. 2 illustrates problems of the conventional static memorycell;

[0017]FIG. 3 shows an embodiment of a static memory cell array;

[0018]FIG. 4 is a timing chart illustrating a reading operation of theembodiment shown in FIG. 3;

[0019]FIG. 5 is a timing chart illustrating a writing operation for theembodiment of FIG. 3;

[0020] FIGS. 6(a) and 6(b) respectively show a static memory cell arrayaccording to an embodiment of the present invention, and a timing chartfor the embodiment of FIG. 6(a);

[0021] FIGS. 7(a) and 7(b) respectively show a static memory cell arrayaccording to an embodiment of the present invention, and a timing chartfor the embodiment of FIG. 6(a);

[0022]FIG. 8 illustrates an embodiment including a shared power source;

[0023]FIG. 9 illustrates another embodiment of a static memory cellarray;

[0024]FIG. 10 is a timing chart illustrating a read operation of theembodiment shown in FIG. 9;

[0025]FIG. 11 is a timing chart illustrating a write operation of theembodiment shown in FIG. 9;

[0026] FIGS. 12(a) and 12(b) show power supply line embodiments forpreventing a voltage drop;

[0027]FIG. 13 illustrates an embodiment in which power supply lines andword lines intersect at right angles;

[0028]FIG. 14 illustrates and embodiment in which the present inventionis applied to a chip powered by two external power sources;

[0029]FIG. 15 illustrates and embodiment in which the present inventionis applied to a chip powered by a single external power source;

[0030]FIG. 16 illustrates a power supply line driving system;

[0031]FIG. 17 is a sectional view of an embodiment of the presentinvention;

[0032]FIG. 18 illustrates a sectional view of another embodiment of thepresent invention;

[0033]FIG. 19 illustrates a sectional view of yet another embodiment ofthe present invention;

[0034]FIG. 20 illustrates a sectional view of still another embodimentof the present invention;

[0035]FIG. 21 shows an embodiment in which the invention is applied to adivided memory cell array;

[0036]FIG. 22 shows an internal circuit of a memory cell of theembodiment of FIG. 21;

[0037]FIG. 23 is a characteristic diagram plotting signal developingtime against supply voltage for the memory cell of FIG. 22; and

[0038]FIG. 24 illustrates an embodiment of a system for driving thedivided power supply lines of FIG. 21.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039]FIG. 1(a) shows an embodiment in which a transistor QP illustratesa means for controlling the connection between an operation voltagepoint VCH of a semiconductor integrated circuit and a static memorycell, for each such cell in the circuit. FIG. 1(b) shows an embodimentin which the transistor QP is added to each row of a memory cell array.FIG. 1(c) shows an embodiment in which the transistor QP is shared amongall cells in the memory cell array.

[0040] For simplicity, all of the transistors in the memory cell areassumed to have a threshold voltage VT of 0.5 V. Therefore, nosubthreshold current will flow through the transistors if the gate andsource voltages are substantially equal.

[0041]FIG. 1(a) illustrates a basic concept of the invention. Betweenthe common source of P-channel MOS transistors QC1 and QC2 and the powersource VCH (or between the higher power supply node of memory cell MCand the power source VCH) is inserted a P-channel MOS Qp, which acts asa switch. The common source of N-channel MOS transistors QS1 and QS2 orthe lower power supply node of the memory cell MC is connected to areference voltage level VSS (ordinarily at the ground voltage of 0 V).

[0042] The memory cell MC, as exemplified herein, is a static memorycell which is composed of MOS transistors having mutually cross-coupledgates and drains, as illustrated. More specifically, the memory cell MCis constructed to include a data storage cell in which the output of oneinverter composed of QC1 and QS1 is connected to the input of the otherinverter composed of QC2 and QS2, and transfer MOS transistors QT1 andQT2 are connected at data storage nodes N1 and N2, respectively. Thearrangement assumes that the power source has a sufficiently highcurrent supplying capability at voltage VCC supplied from the outside,and that the power source for the higher voltage VCH has a low currentsupplying capability. The power source having the low current supplyingcapability suffers from a temporary voltage drop when a current flowsthat is higher than the supplying capability.

[0043] When data are to be written in the memory cell from the data linepair, the voltage VCC is ordinarily applied to one of the data lineswhile the MOS transistor QP is not conducting, whereas a potential of 0V is applied to the other data line. If the word line voltage is at VCCat this time, the voltage (VCC−VT), as dropped by the threshold voltageof QT1 or QT2, is input to one of the data storage nodes N1, N2, whereasa potential of 0 V is input to the other data storage node. With thesesettings, however, the data storage voltage (i.e., the voltagedifference between the nodes N1 and N2) is VCC−VT, an excessively lowlevel of 0.5 V for VCC=1 V and VT=0.5 V.

[0044] After this write operation (that is, after the word line voltageis turned off), QP is turned on to apply a sufficiently high VCH (e.g.,2 V) to the common source. Then, the cross-coupled transistors in thememory cell are enabled to act as a differential amplifier so that oneof the nodes N1 and N2 is charged to VCH while the other is left at 0 V.The data storage voltage thus rises from (VCC−VT) to VCH. Note that QPneed not be timed with the word line activating timing, but is desirablytimed to turn on after the word line voltage is turned off so that nounnecessary current flows from the power source VCH (which has a lowcurrent supplying capability) to the data lines (bit lines) DL and /DLthrough the memory cell.

[0045] Incidentally, the data, as written in the nodes N1 and N2 for thetime period between the time when word lines are turned off to the timewhen QP is turned on, are held by the parasitic capacitances of thenodes N1 and N2, respectively. If the memory cell is continuouslysupplied with VCH by turning on QP for the data holding period or at thestandby time after the memory cell is enabled, as described above, theoperation margin of the memory cell is extended during this period.Moreover, the operation is fast/stable even at the time of reading thememory cell, because the current driving capability of QS1 or QS2 isimproved by the rise of the gate voltage.

[0046] Since the writing operation can be performed with QP off, thememory cell is made dynamic by any write data so that it can be writtenat a high speed with low electric power. If not for the QP (i.e., if VCHwere connected directly to the memory cell) or if QP were turned on inthe course of the writing operation, current would flowdisadvantageously through QP for a long time, requiring higher power, ormaking difficult the data inversion during a writing operation.

[0047]FIG. 1(b) shows an embodiment in which QP is shared among aplurality of memory cells, which reduces the total number of transistorsfor the semiconductor integrated circuit. When memory cell MC1 iswritten with QP1 off, as described above, the data line pair forciblyapplies the voltage of 0 V to the gate of QC1 of MC1 and the voltage of(VCC−VT) (0.5 V) to the gate of QC2, for example. As a result, QC1 isturned on, so that VCH (held by the parasitic capacitance of the commonpower supply line) is discharged to (VCC−VT).

[0048] At this time, a memory cell MC2 on the same word line WL1 issubstantially in a reading operation, but the stored data of MC2 are notaffected, even though the voltage on PL1 drops. The data storage voltageof MC2 only drops from VCH to the voltage of PL1 or to (VCC−VT). Thesensitivity of the differential amplifier in the memory cell isdetermined to about 0.2 V or lower by the offset voltage of the pairingtransistor, and the voltage (VCC−VT) exceeds that sensitivity; thus, thedata are not broken. Specifically, if QP1 is turned on after the end ofthe writing operation, applying VCH to PL1 again, the stored voltage ofMC2 assumes the voltage VCH in the same manner as MC1.

[0049] In this embodiment, only one power feeding line corresponding tothe activated word line may be charged to VCH. Since the remaining,numerous, power supply lines (e.g., PL2) are left at VCH, no chargingoperation begins even if the corresponding charge transistor (QP2) isturned on. In short, the charge on the power supply lines is localizedto reduce power consumption.

[0050]FIG. 1(c) shows an embodiment in which the charged transistor QPis shared among all memory cells, so that the degree of integration isfurther improved over the integration of the foregoing embodiments. Inthis case, however, the voltages of all power supply lines drop,including those of the memory cells at the inactivated word line. Hence,the charge/discharge power for charging those memory cells to VCH may beincreased, or the operation speed may be lowered. However, the area forthe memory cells can be reduced if the power supply lines adjoining theword lines are shared, because the number of wiring lines of the memorycells is effectively decreased by consolidating the power supply lines(PL1 and PL2 in FIG. 1(b), for example) under control of a singletransistor.

[0051] A circuit construction in which the higher power supply node ofthe memory cells of an SRAM is equipped with switch MOS transistors isdisclosed in Japanese Patent Laid-Open No. 60-38796 and Japanese PatentLaid-Open No. 2-108297. However, these disclosures are different inconcept from the present invention because the voltage level to beconnected through the switch MOS is fed to the device itself.

[0052] The following embodiments refer primarily to FIG. 1(b). Bothwrite operations and read operations will be described.

[0053]FIG. 3 is a circuit diagram of an embodiment of the presentinvention, FIG. 4 is a timing chart for a read operation of the FIG. 3embodiment, and FIG. 5 is a timing chart for a write operation of theFIG. 3 embodiment.

[0054] The memory cell is exemplified by a flip-flop type cell composedof P-channel MOS transistors and N-channel MOS transistors. Thethreshold voltage VT of all transistors in the cell is set to a highlevel, such as 0.5 V, such that the subthreshold current can besubstantially neglected. For simplicity, a 4-bit cell array isdescribed, with VCC=1 V and VCH=2 V, and assuming that the SRAM isdriven by a single battery power source of voltage VCC. Thus, thepresent embodiment has the following characteristics:

[0055] (1) The voltages of the cell power supply lines (PL1 and PL2) areswitched according to the operation timing of the cell. Specifically,the voltage of the power supply line of each cell is controlled suchthat the data holding voltage (e.g., 2 V in the FIG. 3 embodiment), whenthe cell is not activated, is determined by the voltage which is appliedfrom the power supply lines of the cell, and such that the voltage levelis higher than the write voltage to be written in the cell from the datalines when the cell is activated.

[0056] (2) The data lines (DL1, /DL1, DL2, and /DL2) operate withreference to a substantially intermediate voltage (i.e., VCC/2=0.5 V) ofthe maximum voltage (e.g., VCC=1 V in FIG. 3) that can be assumed by thedata lines. As a result, the power for charging/discharging the datalines is halved.

[0057] (3) The amplitude of the pulse voltage of the activated word lineexceeds the maximum voltage that can be assumed by the data lines. Inorder to eliminate the influence of the threshold voltage VT of theactivated transistor connected to the word line, the amplitude of thepulse voltage is set by a voltage boosting circuit in the chip, to alevel (VCH) higher by at least VT than the maximum voltage of the datalines. Moreover, the current driving capabilities of QT1 and QT2 can beimproved to speed up the operations by the boosted level.

[0058] A portion of an SRAM or the SRAM chip itself (together termed an“SRAM”) to be incorporated in a microprocessor chip is disabled by anSRAM enable signal CE. The main portion of the SRAM is precharged by aprecharge signal ΦP. For example, the power supply lines (PL1 and PL2)of the memory cell are precharged to the voltage VCH, which has beengenerated by boosting on-chip the external supply voltage VCC. The dropof the data storage voltage in the cell, as caused by a fine leakvoltage in the cell, is blocked by compensation currents from P-MOS QP1and QP2, so that the data storage states of the individual cells areheld.

[0059] In this example, VCH is generated by a voltage converter VC2. Thevoltage VCH is generated to boost the voltage VCC in the chip by using acharge pump circuit for driving the capacitor, so that the currentdriving capability is accordingly low. However, the threshold voltage ofthe transistors in the cell is set sufficiently high (e.g., 0.5 V orhigher) so that the total of the leak currents of the cell, even for anSRAM having a capacity as high as megabits, can be lowered to asufficiently low level, such as 10 μA or lower. As a result, thecompensation currents can be fed to all memory cells from the VCHvoltage boosting circuit. Details of a voltage boosting circuit may befound by reference to page 315 of “VLSI memory” (issued by BAIFUKAN inNovember, 1994). An on-chip voltage boosting circuit, which is suitablefor the present invention and operated by a very low-voltage powersource (such as 1 V), may be found by reference to pages 75-76 of “1995Symposium on VLSI Circuits; Digest of Technical Papers”. The disclosuresof these two documents are hereby incorporated by reference.

[0060] The threshold voltage of the MOS transistors to be utilized inthe voltage boosting circuit of this latter publication is set to about0.6 V, such that a voltage boosting circuit that is operable at a lowervoltage, such as the supply voltage VCC, may be provided if MOStransistors having lower threshold voltages are used. When transistorshaving lower threshold voltages are employed, care should be taken withregard to the subthreshold current. However, the leakage current bytransistors constituting the voltage boosting circuit is small, sincethe transistors are relatively small in number. See also Japanese PatentLaid-Open No. 6-223581, which discloses a circuit construction in whichthe voltage boosting circuit is connected to the higher power supplynode of the SRAM memory cell. The voltage level of the voltage boostingcircuit or its external supply source is connected to the power supplynode.

[0061] For the precharge period during which the SRAM is disabled by thesignal CE, the individual data lines (DL1, /DL1, DL2, and /DL2, whereinthe inverted signal of the paired complementary signals is designated bya slash) are precharged to VCC/2 by the precharge circuit PC. Thus, thevoltage amplitude of the data lines can be halved as compared with theVCC precharge of the prior art. The halved data line voltage eliminatesthe prior art problem of simultaneous writing time of multibit data,because the data line charging/discharging power is halved.

[0062] The precharge voltage VCC/2 is preferably generated from the VCCsource by the voltage converter VC1, as is seen by reference to FIG.4.60, page 324, of the “VLSI Memory” publication mentioned above. Thislevel VCC/2 is prepared in the chip so that it generally has a low loadcurrent driving capability. If one of the data line pair is prechargeddirectly from zero to VCC/2 by the VCC/2 power source at the prechargingtime, a sufficient charge current cannot be supplied, which causes afluctuation in the level VCC/2. This fluctuation is problematic becausethe number of paired data lines is usually as many as 64 or 128 orlarger.

[0063] Thus, each data line is equipped with an amplifier AMP, as shownin FIG. 3. This amplifier AMP quickly amplifies the fine differentialvoltage, appearing on the data line pair at the cell reading time, toVCC. As a result, one of the paired data lines assumes the voltage of 0V, while the other takes the voltage VCC.

[0064] In the next precharge operation, a transistor QEQ is turned on toequilibrate the data line pair automatically to VCC/2. Therefore, a highcharge current need not be supplied from the VCC/2 power source. Anonfluctuating current is required to suppress the data line pair fromfluctuating in voltage level due to the fine leak current if theprecharge period is long. As a result, the packaged VCC/2 power sourcecircuit can be utilized if the AMP circuit is used.

[0065] With additional reference to FIG. 4, data are read out from thememory cells as follows. When the SRAM is enabled by the SRAM enablesignal CE so that a word line (e.g., WL1) is activated and fed with aVCH pulse, all of the cells (MC1 and MC2 in this embodiment) on the wordline WL1 are enabled. In response to a row address signal AX, theactivate signal pulse of that word line is generated by a row addressdecoder XDEC and driver DRV. If the nodes N1 and N2 in the cell MC1 arestored with 0 V and 2 V (VCH), respectively, QT1 and QS1 are turned onto discharge the data line DL1 gradually to 0 V. Since the gate voltagesof QS2 and QC2 are substantially at 0 V, the current flows through QC2and QT2 so that the data line DL1 rises slightly from 0.5 V (VCC/2).Because it takes a long time for this slight differential voltageappearing in the data line pair to rise sufficiently, the pulse isapplied to drive lines SP and SN of the amplifier AMP to amplify thedata lines DL1 and /DL1 quickly to 0 V and 1 V, respectively.

[0066] The degree of integration of the SRAM and the subthresholdcurrent are not seriously affected by the AMP compared to the cells;therefore, the size of the transistors in the AMP can be selected to belarger than those in the cells, and the threshold voltage of the AMPtransistors can be set to a level as low as about 0.2 V, so that fastamplification can be achieved. Moreover, the AMP is enabled by anamplifier driving circuit SPG when the memory cell is activated and thedrive lines SP and SN are held at the same voltage level when in the“unable” (or standby) state, so that the subthreshold current raises noproblems. Moreover, the AMP operates even when the data line pairvoltage level is at about 0.5 V.

[0067] The voltage difference of the data line pair, sufficientlyamplified as described above, is output to the I/O line pair by a readactivate signal ΦR1 of the column address decoder YDEC and driver DRV,so that the output becomes a data output DOUT through a read/writebuffer circuit RWB. In FIG. 3, transistors QR1 and QR2 convert thevoltages of the data line pairs into currents. If these transistors havethreshold voltages of 0.5 V, the current flows through the I/O line,because the data line DL1 has a voltage of 0 V, but not through the /I/Oline because the /DL1 has a voltage of 1 V. The line through which thehigher current flows can be detected within the RWB in the polaritydiscrimination shape of the differential current or voltage by utilizinga resistor R, as shown. Incidentally, if the threshold voltage VT of QR1and QR2 is sufficiently low, such as 0.2 V, even a slight voltagedifference before the amplification of the amplifier AMP can bedetected, so that the speed can be accordingly increased, because themutual conductance is increased for the VT drop so that a higher currentcan flow.

[0068] The node voltage of the memory cell MC1 will be described indetail with additional reference to the reading operation timing chartof FIG. 4. A problem arises if QP1 or QP2 is turned on in the “active”period or if the QP1 or QP2 is eliminated to apply VCH directly to thepower supply line PL1 or the like. When VCH is an external voltagehaving a high current driving capability, a large direct currentcontinues to flow from all cells on PL1, while the voltage is beingapplied to the word lines, so that the power becomes high.Alternatively, when the power source voltage VCH boosted in the chip isused, as in the present embodiment, the current driving capability ofthe voltage boosting circuit becomes short, lowering the level of theVCH. As a result, the data storage voltage of the inactivated cells onPL1 also drops. Once the voltages of all power supply lines drop, a longtime is required to recover the level of VCH, because the totalparasitic capacitance of the power supply lines is high. As a result,the cycling time of the SRAM is retarded.

[0069] At the cell disable time, therefore, all power supply lines areforcibly set to VCH (2 V) by the precharge signal ΦP. For the activeperiod, however, the individual power supply lines are disconnected fromthe VCH generator. The individual power supply lines come into asubstantially floating state so that the level of the VCH is held bytheir parasitic capacitances. When the cell is activated (for thereading operation in this case), the cell node N1 takes the value of 0V, turning on QC2. Since the sources of these transistors are connectedto PL1, the floating voltage of PLI drops from VCH so that the nodes N1and N2 are charged to the high level. However, the node N1 remains at 0V because it is forcibly fixed there by the voltage of DL1. On the otherhand, the gate of QT2 (which has the same potential as WL1) assumes thevoltage of 2 V, and /DL1 assumes the value of 1 V so that QT2 is turnedon. As a result, node N2 continues to be charged by QC2 until thevoltages of PL1 and N2 are equalized, so that PL1 takes 1 V. It is thusapparent that the power supply lines to be discharged to 1 V arelocalized. Specifically, the localized lines are limited to PL1, and PL2corresponding to the inactivated word line is not discharged, but isleft at VCH.

[0070] In the preferred embodiment, there are many power supply lines,only one of which is discharged so that the useless charge/dischargepower of the prior art is eliminated. Moreover, the power supply linesto be charged by the incorporated VCH generator are localized andreduced to one in number, so that the VCH generator can be simplydesigned.

[0071] In the write operation illustrated in FIG. 5, the cell MC1 iswritten by applying a differential voltage to the common I/O line pair.In the illustrated example, data inverted from those in MC1 are to bewritten into MC1. The voltages of 1 V and 0 V are applied to the dataline pair DL1 and /DL1, respectively, and further directly to the cellnodes N1 and N2. As a result, the voltage difference of 1 V is writtenin the nodes N1 and N2.

[0072] After the word line WL1 is turned off from 2 V to 0 V, theprecharge operation is executed with the signal ΦP. Then, the nodevoltage difference of 1 V is amplified to 2 V by the amplifications ofthe cells themselves, because the cell power supply line PL1 is at 2 V.This high voltage becomes the subsequent data holding voltage. In thewrite operation, the line PL1 must be fed with the voltage VCH after WL1is turned off to minimize the capacitance to be charged by the VCHgenerator.

[0073] The stored data of the other memory cells MC on the activatedword line WL1 are not broken by the foregoing operations. When thememory cell MC1 is read or written, it transfers data to and from theI/O line pair. During this transfer, a reading operation like that ofFIG. 4 is performed with respect to MC2 and the data line pair DL2 and/DL2 because the activate pulse is always applied to the line WL1 of thecell MC2. As a result, if VCH is applied again, even when PL1 is changedfrom 2 V to 1 V, the two nodes in MC2 are restored to VCH (2 V) and 0 V.Moreover, the stored data in memory cells MC3 and MC4 on the inactivatedword line WL2 are not adversely affected in the least. At most, only anegligible junction leak current, if any, flows through the transistorsin MC3 and MC4, because the threshold voltage VT is sufficiently high toprevent a subthreshold current. Thus, the voltage VCH at the prechargetime is held in the power supply line PL2.

[0074] The amplitude of the pulse voltage of the activated word line isVCC and, if the maximum (VD) to be taken by the data lines is set to(VCC−VT) or less, the word voltage need not be generated from thevoltage boosting power source VCH. In addition, the influence of thethreshold voltage VT of the transistors QT1 and QT2 in the memory cellcan be eliminated at the cell writing time or the like, so that thedesign can be facilitated. FIGS. 6(a) and 6(b) show an embodiment ofthis case.

[0075] FIGS. 6(a) and 6(b) respectively show a circuit diagram and awaveform timing chart for the portion of the FIG. 3 embodiment relatingto the memory cell driving system. However, the embodiment of FIG. 6(a)and 6(b) is different from FIG. 3 with respect to the precharged circuitPC and the read/write circuit RWC. Moreover, the signal level of theword line is set to the reference voltage level of 0 V and the supplyvoltage VCC, and the higher power supply node of the inactivated memorycell is set to VCH (2 VCC) in the present embodiment, whereas the lowerpower supply node of the memory cell is set to the reference voltagelevel of 0 V. On the other hand, the precharge voltage of the data linesis set to a level that is higher than the reference voltage level by atleast the sensitivity voltage of the memory cell. The sensitivityvoltage, or “sensitivity”, of the memory cell may be defined as theminimum voltage difference necessary for inverting the state of the datastorage cells or the flip-flop circuit by the voltage difference whichis applied between the lines DL and /DL of FIG. 1, for example.

[0076] In order to exemplify the sensitivity voltage with respect to thevoltage difference between DL and /DL, the precharge voltage of the datalines may be one-half or more of the sensitivity voltage. Since thesensitivity voltage of the memory cell is usually lower than 0.2 V, areference voltage level VR is set to 0.2 V to afford a margin, and theprecharge voltage level of the data lines is set to 0.2 V. In otherwords, the maximum of the voltage amplitude to be assumed by the datalines according to this embodiment is reduced to the low voltage VR nearthe sensitivity voltage of the memory cell itself, or lower than thethreshold voltage VT (0.5 V). The voltage amplitude of the data lines ofthe memory cell is minimized so that the low-power operations can beperformed at a correspondingly high speed. As a result, the data linepair can be precharged by the reduced voltage power source, which isillustratively composed of a comparator using QL1 and VR as shown. Thedata storage voltage level of the memory cell can be sufficientlydeveloped to VCH (2 V).

[0077] The reading operation according to this embodiment will bedescribed with additional reference to FIG. 6(b). Initially, all of thecell power supply lines are precharged to VCH by the precharge signalΦP. At the end of this precharge operation, a pulse having the amplitudeVCC (1 V) is applied to the activated word line WL1. If the nodes N1 andN2 in the cell are at 0 V and VCH, for example, QT1 is turned on todischarge data line DL1 from 0.2 V to 0 V. Since QT2 is on but QS2 isoff, the charge of the node N2 is distributed to the other data line/DL1 so that the line /DL1 slightly rises from 0.2 V to V. This rise isslight because the data line capacitance is 100 times or more as largeas the in-cell node capacitance.

[0078] At this time, the voltage of the node N2 is discharged from 2 Vto V. The differential voltage thus appearing in the data line pair isextracted as the cell reading data from the I/O line pair through theread transistors QR1 and QR2. In order to achieve a large gain,P-channel MOS transistors are preferably used for QR1 and QR2. By thisseries of operations, power line PL1 finally drops to V.

[0079] When the precharge operation is next started, however, the valueV is higher than the sensitivity of the cell itself, so that V isnormally amplified to VCH by the cross-coupled P-channel MOS transistorsQC1 and QC2. If the voltage difference V between the nodes N2 and N1 issmaller than the sensitivity, however, V is not normally amplified atthe precharge time, and the inverted data may be held.

[0080] Incidentally, the writing operation is performed by applying adifferential voltage of 0.2 V to one of the paired data lines, asselected from the I/O line pair, and a voltage of 0 V to the other dataline, and then by setting the power supply line PL1 to 2 V by aprecharge operation as in the reading operation.

[0081] FIGS. 7(a) and 7(b) show an embodiment in which a high datastorage voltage is achieved by pulse-driving the higher and lower powersupply nodes of the memory cell at the precharge time. FIG. 7(a) is acircuit diagram, and FIG. 7(b) is a waveform timing chart correspondingto the circuit diagram. FIGS. 7(a) and 7(b) thus relate to the memorycell driving system of the entire SRAM, and the illustrated embodimentdiffers from that of FIG. 3 in that the lower voltage level of thememory cell can be changed depending upon whether the memory isactivated. More specifically, the lower power supply node of the memorycell is set, when inactivated, to the reference voltage level of 0 Vand, when activated, to a voltage level that is dropped by at least thesensitivity voltage level of the memory cell from VCC/2. In thisembodiment, moreover, the signal level of the word lines is set to thereference voltage level of 0 V and the supply voltage VCC, and theprecharge voltage level of the data lines is set to VCC/2. However, thehigher power supply node of the inactivated memory cell is set to VCH (2VCC).

[0082] Although the precharge voltage of the data lines is as low as 0 Vin the embodiment of FIGS. 6(a) and 6(b), the present embodiment isfeatured in that the precharge voltage of the data lines is at VCC/2.Thus, the read transistors QR1 and QR2 of FIG. 6(a) are replaced byN-channel MOS transistors suited for higher operations. Moreover,amplifications can be made at a higher speed because two kinds ofamplifiers (QS1 and QS2, and QC1 and QC2) in the cell are enabled at theinitial stage of the precharge.

[0083] Assuming that VCH=3 V, VCC=1.5 V, VT=0.5 V, and VR=0.2 V, andfurther that a VCC/2 precharge circuit PC like that of FIG. 3 isconnected to each data line pair, all data lines are set to 0.75 V, thepower supply lines (PL1, etc.) are set to 3 V, and the power supplylines (PL1′, etc.), which are connected to the N-channel MOStransistors, are set to 0 V, because a transistor QL2 is cut off for theprecharge period by a transistor QL3 so that the line PL1′ is set to 0 Vby a transistor QL4. Moreover, the nodes N1 and N2 in all cells are setto 3 V or 0 V in accordance with the stored data.

[0084] After the end of the precharge period, the line PL1 is held at 3V. On the other hand, the line PL1′ is developed toward VCC by aresistor R′. When the voltage ((VCC/2)−VR, or 0.55 V) is reached,however, any further rise is suppressed by the comparator using thevoltage of ((VCC/2)−VR) as the reference voltage in the voltage limitingcircuit composed of QL2.

[0085] At the same time, the lower node N1 takes 0.55 V. Resistor R′ isset at a relatively high resistance to suppress the power consumption,but can be replaced by a MOS transistor.

[0086] When the word voltage develops, transistors QT1 and QS1 areturned on because the node N1 is at 3 V, whereas the node N1 is at 0.55V, so that the data line DL1 is discharged. With the difference VRbetween the lines DL1 and PL1′, therefore, the line DL1 is finallydischarged to the voltage 0.55 V of the line PL1. Since QS2 is off, onthe other hand, the charge on node N2 is released through QT2 to theline /DL1, as described above, and the node N2 and the line /DL1 takessubstantially equal voltages of (0.75 V+V). This voltage difference,appearing on the data line pair, is extracted to the I/O line pairthrough the activated read circuit connected to each data line.

[0087] By the subsequent precharge, the voltage difference of about 0.2V between the nodes N1 and N2 is amplified quickly to 3 V. When the linePL1′ assumes 0 V, both QS1 and QS2 are turned on because N1 has been at0.55 V, whereas N2 has been a voltage level slightly higher by V than0.75 V, so that a voltage difference of about 0.2 V between N1 and N2 isamplified by the cross-coupled amplifiers QS1 and QS2. This voltagedifference is also amplified by the other cross-coupled amplifiers QC1and QC2.

[0088] In the embodiment of FIGS. 6(a) and 6(b), at the initial stage ofthe amplification in the cell at the start of the precharge operation,the amplifier composed of QS1 and QS2 is off, and the amplification iscarried out only by the amplifier composed of QC1 and QC2. Therefore,the embodiment of FIGS. 6(a) and 6(b) has a rather low speed. However,the present embodiment has a higher speed because both of theseamplifiers contribute to the amplifying operation at the initial stageof the amplification.

[0089] The writing operation may be performed by applying 0.75 V and0.55 V to the respective members of the activated data line pair inaccordance with the write data. Further, power supply line PL1′ iscontrolled to 0.55 V at the cell activating time as in the readingoperation.

[0090] According to the present embodiment, the drive can be made evenby a VCC/2 voltage generator, packaged in the chip, because the voltageamplitude of the data lines is extremely small (about 0.2 V). As aresult, the amplifier AMP of FIG. 3 can be eliminated, so that the chipcan be made smaller. Further, since the data line pair operates in thevicinity of VCC/2 at all times, the stress voltage to the transistorsfor the precharge circuit or the read circuit (QR1 and QR2) on each dataline can be halved to improve reliability.

[0091] Moreover, the precharge voltage of the data lines need not alwaysbe at VCC/2. Instead, the precharge voltage of the data lines may be setto a level higher than the sensitivity of the in-cell amplifier withrespect to the PL1′ voltage when activated.

[0092] On the other hand, the present embodiment connects the powersource circuit constituted by QL2 and QL3 and the comparator to eachpower source drive line PL′ (PL1′ and PL2′) of the in-cell N-channel MOStransistor because the time period for raising PL1′ to 0.55 V isshortened to speed up the access. To reduce the chip size, however, thiscircuit can be shared with another power supply line as shown in FIG. 8.For the precharge period, the common power supply line PLC is alwaysfixed at ((VCC/2)−VR) by the common power supply circuit, but all of thepower supply lines PL1′ to PLn′ are at 0 V. When PL1′ is to beactivated, a signal ΦX1 is decoded to 0 V by the external address sothat the line PL1′ is disconnected from PLC. Afterward, the signal ΦPgoes to VCC to discharge the line PL1 to 0 V.

[0093]FIG. 9 shows an example of applying the teachings of the inventionto the memory cell drive system for the entire SRAM, in which thevoltage of the data lines takes a level in the vicinity of the VCC atthe reading time. The FIG. 9 embodiment is different from that of FIG. 3with regard to the pre-charge circuit PC and the read/write circuit RWC.

[0094] In this embodiment, the signal level of the word lines is set tothe reference voltage level of 0 V and the supply voltage VCC, thehigher power supplying node of the memory cell when inactivated is setto VCH (2VCC), and the lower power supply node of the memory cell is setto the reference voltage level of 0 V. Moreover, the precharge voltagelevel of the data lines is set to the VCC.

[0095] Each data line is connected to the transistors QD1 and QD2, whichact as loads for the activated cell, and to the transistor QEQ, forequalizing the data line pair voltage. This circuit is the prechargecircuit PC of this embodiment. Its operations will be described nextwith reference to the reading timings of FIG. 10.

[0096] For the precharge period, the data line pair is at VCC (1 V), andPL1 is at VCH (2 V). Here, it is assumed that the data-line pair DL1 and/DL1 are activated by a column address activate signal ΦRW1 (from 1 V to0 V) and that the word line WL1 is activated to apply pulses of 0 V to 1V. If the node N2 is at 2 V, a direct current flows between QD1, QT1,and QS1 so that a slight ratio voltage VS (of about 0.2 V) appears inthe line DL1. On the other hand, the node N1 is at about 0 V so that QS2is off, and QT2 is also off as apparent from its voltage relation.Therefore, no current will flow in the paths between QD2, QT2, and QS2because the voltage of the node N1 is more or less developed by theratio action. Thus, the sizes of the transistors in the cell aredesigned to set that voltage to VT or less.

[0097] As a result, the differential signal of VS appears on the dataline pair. This voltage is transmitted not through the complicated readcircuit, as shown in FIG. 3, but directly to the I/O line pair so thatit is read out to the outside, because it is the ratio voltage. Here,QS2 and QT2 are always off so that the charge, as stored in the node N2,is not released. In short, the voltage of PL1 is left at 2 V.

[0098] Even if the current driving capability of the VCH voltageboosting circuit, as incorporated in the chip, is not extremely high, nocurrent will flow through the load PL1 of the voltage boosting circuit.As the case may be, therefore, a direct connection can be made byeliminating QP1. However, this elimination can be made only for thereading operation. The elimination of QP1 is difficult for the writingoperation, as will be described with reference to FIG. 11.

[0099] When a voltage of 1 V is written in one DL1 of the data line pairfrom the I/O line pair, whereas the voltage of 0 V is written in theother line /DL1, the node N1 in the cell is switched from about 0 V to0.5 V because the threshold voltage of QT1 is at 0.5 V, whereas thevoltage of WL1 is at 1 V. Thus, the node N1 takes the voltage which isdropped by the threshold voltage. On the other hand, the node N2 isswitched from 2 V to 0 V because QT2 is turned on, so that the node N2is discharged to the voltage of the line /DL1. As a result, QC1 becomesmore conductive than QC2 so that the line PL1 in the floating state isdischarged to the level of 0.5 V, which is forcibly fed from the dataline to the node N1. Therefore, the line PL1 has to be charged again to2 V by the subsequent precharge.

[0100] If the line PL1 has a high voltage drop, the corresponding chargehas to be supplied by the boosted voltage (VCH) generator to PL1 so thata heavy load is exerted upon the voltage boosting circuit. As a result,the area or power consumption of the VCH generator itself is increased.FIG. 12 shows a load circuit for suppressing the voltage drop to thevicinity of VCC.

[0101] In FIG. 12(a), QP is turned off, but QR is turned on, for thetime period in which the cell is activated. The voltage of the powersupplying lines is switched from VCH to VCC so that one in-cell node(e.g., N1) is not dropped to 0.5 V, as shown in FIG. 11, but suppressedat VCC (1 V). In FIG. 12(b), the design is simplified by eliminating theprecharge pulse /ΦP. The N-channel MOS transistor QR is used, which hasa lower threshold voltage (about 0.2 V) than those of the remainingtransistors. Because of the diode connection, the transistor is turnedon when the voltage of the power supply line becomes lower than(VCC−VT), i.e., 0.8 V or less, so that any further voltage drop can beprevented. In other words, one cell node is not dropped to 0.5 V, asshown in FIG. 11, but suppressed within 0.8 V. This transistor QRprevents, at the pulse timing when the QP is off for a long time, thevoltage level of the floating line PL1 from being excessively lowered bythe diffusion layer leakage current in the cell, thereby to play a rolein extending the voltage margin of the cell.

[0102] Premising the voltage applications of FIGS. 10 and 11, inaddition to the construction in which the word lines and the powersupply lines are arranged in parallel as shown in FIG. 9, the word linesWL1 and WL2 and the power supply lines PL1 and PL2 may be orthogonallyarranged, as shown in FIG. 13. When the cells on the WL1 are read out,for example, the voltage (VCH) level of all of the power supply lines isunchanged because all of those cells perform operations similar to thoseof FIG. 10. In the writing operation, however, only the power supplylines belonging to the activated data-line pair are changed.

[0103] If the combined pulse voltage of 1 V and 0 V (corresponding tothe write data) are applied to the data line pair DL1 and /DL1 (althoughomitted as apparent from the drawing), the cell MC1 performs anoperation similar to that of FIG. 11 so that the voltage of the line PL1drops from 2 V to 0.5 V. Since the cell MC2 performs an operationsimilar to that of FIG. 10, the voltage VCH of the line PL2 isunchanged.

[0104] Whether the arrangement of the word lines and the power supplylines is parallel or orthogonal depends upon the layout and area of thecells. The construction of FIG. 9 is disadvantageous in that the layoutmust have different wiring layers so that the power supply lines are notshorted to the data line pair, but is advantageous with regard to thelow noise.

[0105] If a pulse is applied to the line WL1 to write the cell MC1, suchthat a large voltage change occurs in the line PL1, a read signal fromthe cell MC2 appearing on the data line pair DL2 and /DL2 is so finethat the operation of the cell MC2 is seriously susceptible to theinfluences of noise. Since the data line pair is arranged at a rightangle with respect to the line PL1, though, the noise, which is causedthrough the coupling capacitance by the voltage change in the line PL1,is canceled in the data line pair. Thus, the merits and demerits arecontrary in FIGS. 13 and 9. As a result of the voltage fluctuation ofthe line PL1, for example, a differential noise is made in the adjoiningdata line pair (DL2 and /DL2). In this case, however, the noise can becanceled if the data line pair is transposed at a midpoint, as is wellknown in dynamic memory cells.

[0106] The foregoing embodiments are premised by generating the voltageVCH in the chip from the power source from which the VCC has beenboosted. This is intended to realize a VCC single power source operationthat is convenient for the user. However, VCH may be a chip externalpower source itself, as exemplified by the two external power sources(VCC1 and VCC2) shown in FIG. 14. This chip is assumed to include aninput/output interface circuit INTF, and a core CORE such as a staticmemory SRAM and an arithmetic circuit (e.g., a microprocessor MPU).

[0107] In order that the INTF may warrant the existing logic interfacelevel, an element having a relatively large size is operated by thehigher voltage (VCC1). On the other hand, the CORE determines theperformance (e.g., speed or power) and area of the chip, and its mainportion is given a higher performance by using a small-sized element tobe operated by the lower voltage (VCC2). The elements in the CORE aregenerally finer than those in the INTF.

[0108] In this chip, VCC1 may be deemed as the VCH in the foregoingembodiments. Thus, the entire chip is operated by the two power sources,but the problem of the output level fluctuation accompanying theinternal power source operation is eliminated to facilitate the design.

[0109]FIG. 15 shows an example in which FIG. 14 is applied to a chiprealized with a single power source. In the chip in which the mainportion of the CORE is operated by the internal power source (VCC2)dropped from the external single power source (VCC1), the VCC1 may bedeemed as the VCH discussed above.

[0110] In the foregoing embodiments, the memory cells have been assumedto be of the CMOS type. Since, however, a differential amplifierfunction in the memory cell is applied, the present invention may haveas few as one latch type cross-coupled amplifier in the memory cell. TheP-channel MOS transistors QC1 and QC2 may be replaced by the well-knownhighly resistive polysilicon loads. This is because the nodes N1 and N2can be developed to VCH so that they can be amplified by thecross-coupled N-channel MOS transistors QS1 and QS2. Moreover, thethreshold voltage VT of the N-channel transfer transistors QT1 and QT2(which have the transfer function in the memory cell) may be lower thanthe VT of the remaining transistors in the memory cell (such as 0.2 V).

[0111] The effective gate voltages and the driving current of QT1 andQT2 are increased by the drop of VT at the activated time so that a fastoperation can be achieved. In order to eliminate the subthresholdcurrent through QT1 and QT2 at the inactivated time, however, a bias hasto be made such that the word lines, i.e., the gates of QT1 and QT2 inthe inactivated state, may be lowered from 0 V to a negative voltage,e.g., −0.2 V. If the gate voltage and the source voltage are designatedat VG and VS, respectively, the effective gate voltages of the QT1 andQT2 at the inactivated time are expressed by (VG−VS−VT), i.e., −0.4 V orless for VG, VS, and VT=−0.2 V or less, 0 V and 0.2 V, respectively. If,on the other hand, the minimum of VT at which the subthreshold currentcan be ignored is 0.4 V, the effective gate voltage of the transistorhaving a VT of 0.4 V under the normal bias conditions is −0.4 V, for VG,VS and VT=0 V, 0 V and 0.4 V, respectively. As a result, a lowereffective gate voltage is applied to the system combining theaforementioned low VT and the negative voltage gate, so that nosubthreshold current will flow. In this case, the activated word voltageis pulsating from −0.2 V in the inactivated state to VCC or higher.

[0112] Although it has been assumed that the P-channel and N-channeltransistors in the memory cell have equal VTs of 0.5 V, this assumptionis not essential. Since the N-channel transistor is important fordetermining the read current to the data lines, its VT is set to thelowest level, e.g., 0.4 V as no problem is raised by the subthresholdcurrent. Since, however, the P-channel transistor has a main role ofcharging the fine capacitance in the memory cell and may have a somewhatlow speed, its absolute value may be set to 0.4 V or higher, e.g., 0.6V. For simplicity, on the other hand, VCH has been assumed to be twotimes as high as VCC, but it may be higher than VCC so long as it islower than the breakdown voltage of the transistor (such as the gatebreakdown voltage).

[0113] There is another method of charging the power supplying lines ata high speed while the sensitivity in the memory cell is enhanced. Thecircuit in which the transistors are cross-coupled in the memory cell,as described above, may be deemed as a differential amplifier, and notonly the offset voltage but also the capacitance difference between thenodes N1 and N2 exerts an influence upon the sensitivity of thedifferential amplifier. Depending upon the layout of the memory cell,the capacitance difference may occur if a high density is preferred, andthe sensitivity is degraded for a large capacitance difference. Inshort, immediately before the amplification, a larger voltage differenceis required between the nodes N1 and N2.

[0114] The sensitivity according to that capacitance difference is worsefor the higher speed at which the power supplying line (e.g., PL1) isdeveloped to the VCH. This problem can be solved at the two stageamplifications, as shown in FIG. 16. Specifically, two transistorshaving drastically different channel widths (e.g., ten times) areconnected in parallel to each power supply Line (e.g., PL1). The signalΦP is applied to turn on the transistor (QP1) having a small channelwidth at first, thereby to charge the power supply line gradually. Afterthe amplification is made, and until a large voltage difference isattained between the nodes N1 and N2, a signal ΦP′ is applied to turn onthe transistor (QP1′) having a large channel width to effect thecharging operation at a high speed.

[0115]FIG. 17 shows a section of an embodiment of the present invention.As embodied in the present embodiment, the switch MOS (QP) and the PMOStransistor of the memory cell are formed in the n-wells, and thepotentials of these wells have to be set to VCH so that the source ordrain electrodes of those transistors may rise to VCH. At this time,moreover, the substrate may be of the P-type when the potential of then-well for making the PMOS transistor of the peripheral circuit is to beset to VCC.

[0116]FIG. 18 is a section of another embodiment of the presentinvention. Since the high voltage VCH is applied in the presentembodiment to the switch MOS and the PMOS transistor of the memory cell,the breakdown voltages are developed by making the gate oxide of thoseMOS transistors thicker than those of the peripheral circuit. The MOStransistor of the peripheral circuit has a thin oxide to have a hightransconductance so that it can effect operation at a high speed.

[0117]FIG. 19 is a section of another embodiment of the presentinvention. In the present embodiment, the switch MOS and the PMOS of thememory cell are not separated as when the switch MOS is attached to eachmemory cell, as shown in FIG. 1(a). In this case, the wells for formingthe two MOS transistors may be set to the voltage VCH.

[0118]FIG. 20 is a section of another embodiment of the presentinvention, in which the present invention is formed over an n-typesubstrate. When the present invention is to be applied to the n-typesubstrate, the peripheral circuit, the switch MOS and the PMOS of thememory cell cannot be separated. As embodied in the present embodiment,therefore, there is formed in the switch MOS and the PMOS of the memorycell a common deep p-well, in which an n-well can be formed to changethe peripheral circuit and the voltage level.

[0119] In order to exploit the advantages of the present invention tothe maximum, additional devices are desired for the memory array and theperipheral circuit. FIG. 21 shows an embodiment which is applied to theSRAM portion in the chip or to the one-chip SRAM. The memory portion isdivided into a plurality of memory arrays (MA1, MA2, - - -). Global wordlines (GL1, . . . , GLn) are wired over the plurality of memory arrays.The memory array is composed of a plurality of (mxn) memory cells MCwhich are arranged in a matrix configuration such that (m) memory cellsare arranged in the direction of sub-word lines (WL11, - - -, and WLn1,WL12, - - -, and WLn2, - - -, and so on), whereas (n) memory cells arearranged in the direction of data lines (DL11 and /DL11, - - -, DL12 and/DL12, - - -, and so on). Sub-power supply lines (PL11, - - -, and PLn1,PL12, - - -, and PLn2, - - -, and so on) for applying the boostedvoltage VCH to the higher power supplying nodes of the plurality ofmemory cells through switch MOS transistors (QPL11, - - -, and QPLn1,QPL12, - - -, and QPLn2, - - - and so on) are wired to make individualpairs with the aforementioned sub-word lines. Incidentally, thesesub-word lines can be read merely as word lines when they are made tocorrespond to the aforementioned embodiment.

[0120] Now in the system based upon FIG. 9, the threshold voltage VT ofthe MOS transistors (QC1, QC2, QS1 and QS2) composing the data storagecells of the memory cell MC is set to 0.5 V, and the VT of the transferMOS transistors (QT1 and QT2) is set to 0.2 V, as shown in FIG. 22.Specifically, the MOS transistors, as contained in the memory cell, areset to such a threshold voltage that the subthreshold current will notraise a problem in the entire SRAM, but the transfer MOS transistors areset to such a threshold voltage as requires attention. Moreover, thepower source VCC to be supplied to that SRAM from the outside is set to1 V; the boosted voltage level VCH, which is generated from the VCC bythe voltage converter VC2, is set to 2 V (=2VCC); and the negativevoltage of −VWB, which is generated from the same VCC by a voltageconverter VC3, is set to 0.2 V.

[0121] In order to activate one sub-word line WL11, that is, to applythe cell enabling pulse, which will develop from the aforementionednegative voltage of −VWB (e.g., −0.2 V) to VCC (1 V) ,to WL11, forexample, a global word line GL1 and a control line RX1 may be activatedby the address signal. For activating this control signal RX1, there isutilized a memory array activate signal Φsr1 which is generated by theYDEC.DRV and a timing control circuit TC for activating the memory arrayMA1 substantially. Specifically, it is sufficient to apply the pulse,which develops from −VWB to the VCC by a level converter LCB receivingthe signal Φsr1, to the RX1 and to apply the pulse, which develops fromthe VCC to the −VWB by another level converter LCB connected to theGL12, to the GL1.

[0122] The global word line GL1 is activated from the row address AX bythe row address decoder/driver XDEC.DRV. At this time, the remaining GLlines (or global word lines) and the remaining RX lines are left at VCCand −VWB, respectively. In the switch MOS activate signal group (ΦP1,ΦP2, - - -), on the other hand, only the signal ΦP1 is activated byanother level converter LCA into the pulse to develop from 0 V to VCH,whereas the remaining signals are left at 0 V. As a result, the switchMOS to be connected to the lines PL11, - - -, and PLn1 are turned off,but the corresponding switch MOS group of the inactivated memory arrayis left on. In order to develop the signal ΦP1 from 0 V to the VCH,there is utilized a memory array activate signal Φsp1 which is generatedby the YDEC.DRV and the timing control circuit TC2 to activate thememory array MA1 substantially. Thus, the memory cell (MC) group on theWL1 is enabled to perform the aforementioned operations.

[0123] Transistors Q′D1 and Q′D2 on each data line pair are accelerationtransistors for precharging the voltage of the data line pair to VCC athigh speed. Moreover, the circuit RWC is a read/write circuit to beactivated by a column read activate signal (ΦRY1) similar to that ofFIG. 2, and all of these circuits use a low VT. N-channel and P-channelMOS transistors are connected in parallel to be activated by the columnwrite activate signals (ΦWY1 and /ΦWY1) for performing the writingoperations from the I/O line to the data lines at a high speed.

[0124] By the multi-division/partial-drive of the word lines and thepower supply lines thus far described, the load upon the packaged VCH or−VWB generator can be lightened to facilitate the single power sourcedesign better, because the power supplying lines and the word lines, asrequired for supplying electric power to the VCH and −VWB due to thevoltage fluctuation according to the operations, are localized on thesub-power supply lines and the sub-word lines WL11.

[0125] This embodiment is advantageous in that the increase in the areaaccompanying the division is small because it is sufficient to add onlyone switch MOS to each power supplying line. Since the signal ΦP1 is ahigh voltage (VCH) pulse, however, the power for charging/dischargingthe gate capacitance of the numerous switch MOS transistors connected tothat line is relatively increased.

[0126]FIG. 23 plots the operating voltage margin of the memory cell ofFIG. 22. In FIG. 23, the abscissa indicates the supply voltage VCCsupplied from the outside, and the ordinate indicates the signaldeveloping time τ which is defined by the time period from the instantwhen the word line WL is activated (from 0 V to the VCC) to the instantwhen the potential difference between the data lines DL and /DL reaches100 mV. The signal developing time τ is the better if it is the shorter.

[0127] The conventional curve (solid circles) plots the characteristicsof the conventional memory cell in which it is assumed that all six MOStransistors in the memory cell of FIG. 22 have equal threshold voltagesVT=0.75 V and in which the source side power supply nodes (i.e., thehigher power supply nodes of the memory cell) of the QC1 and QC2 areconnected directly to the supply voltage VCC. In this conventionalconstruction, the MOS transistors have a high VT so that thesubthreshold current raises no substantial problem. It is, however,found that the signal developing time τ abruptly increases for a supplyvoltage less than 0.8 V, so that the conventional construction cannotoperate. In other words, when the supply voltage VCC becomes lower thanthe threshold voltage VT of the MOS transistors used, the memory cellfails to operate substantially by the increase in the developing time z.

[0128] On the other hand, the use of the memory cell of the presentinvention, as shown in FIG. 22, allows the operations at a lower supplyvoltage. The curve, as indicated by open circles in FIG. 23, iscalculated by setting the threshold voltage of the QC1, QC2, QS1, andQS2 that constitute the data storage cell in the memory cell of FIG. 22to 0.75 V, and the threshold voltage of the transfer MOS transistors QT1and QT2 to 0.2 V. Moreover, the boosted voltage VCH is calculated forthe two cases of 2VCC and 3VCC, the calculated points of which areplotted by circles and squares, respectively. It is understood that thisexample operates for τ=10 ns even if the supply voltage becomes lowerthan the threshold voltage of the MOS transistors of the data storagecell up to about 0.5 V.

[0129] In other words, according to the present invention, there isprovided a method of constructing an SRAM which can operate at a voltagelower than the threshold voltage of the MOS transistors of the datastorage cell, even though the threshold voltage cannot be made lowerthan a predetermined value (e.g., 0.5 V) by the restriction of thesubthreshold current. Since the threshold voltage of QT1 and QT2 is setin FIG. 22 to a value such as 0.2 V, which raises the problem of thesubthreshold current, the lower signal level of the word lines is set to−VWB so that no subthreshold current may flow through the QT1 and QT2when the memory cell is not activated. When MOS transistors havingthreshold voltages of 0.5 V are used so as not to raise the problem ofthe subthreshold current in the QT1 and QT2, the higher signal level ofthe word lines may be boosted sufficiently to enhance their drivingabilities.

[0130] Moreover, a sufficient low-voltage operation can be achieved ifthe load MOS transistors on the data lines or the VT of the MOStransistors in the read/write circuit RWC, as shown in FIG. 21, is madesufficiently low (e.g., 0.2 V or less). The remaining peripheraldrive/logic circuits are enabled to exhibit their effects at asufficiently low VT, i.e., a sufficiently low VCC by using thesubthreshold current which is described in the aforementioned entitled“VLSI Memory”. As a result, the chip entirety can operate even at theVCC lower than the VT of the in-cell cross-coupled MOS transistors.

[0131] The present invention is advantageous especially in that it isoperated by a low supply voltage, such as a battery. Specifically, theSRAM can be operated by a solar cell which has a supply voltage of about0.5 V. Moreover, the effect of reducing the power consumption isprominent because the operating voltage can be lowered.

[0132]FIG. 24 shows another embodiment for reducing the powerconsumption although its area is rather enlarged. For simplicity, thereis shown only the WL11 and PL11 of FIG. 21. Although the MOS transistorsPL11 to PLn1 of FIG. 21 for switching the VCH are simultaneouslycontrolled by the single signal ΦP1, the switch MOS and a levelconverter for controlling the gate of the former are added in FIG. 24 toeach of the divided power supply lines. When the WL11 is activated sothat an enable pulse is applied, for example, the gate of the QPL1 isswitched from 0 to the VCH so that the QPL1 is turned oft. As a result,only one gate capacitance is to be driven by the high voltage (VCH), sothat the power consumption is reduced. At this time, the gates of theremaining switch MOS transistors are left at 0 V.

[0133] As is now apparent from the foregoing embodiments, the presentinvention can realize a semiconductor integrated circuit in which areincorporated fast static memory cells having a wide voltage marginwithout increasing current consumption even in a low-voltage operation.

[0134] Various modifications of the foregoing invention will becomeapparent to those of ordinary skill in the art. All such modificationsthat basically rely upon the teachings through which the presentinvention have advanced the state of the art are properly consideredwithin the spirit and scope of the following claims.

We claim:
 1. A semiconductor integrated circuit, comprising: a staticmemory cell including MOS transistors having gates and drainscross-coupled to each other, wherein said cross-coupled MOS transistorsconduct substantially no electric current between their drains andsources when their respective gates and sources have equal voltages; aswitch connecting a power supplying node of said static memory cell to afirst supply voltage, wherein said switch is open when said staticmemory cell is activated, wherein said switch is closed when said staticmemory cell is inactivated; and wherein said first supply voltage ishigher than the maximum voltage of a data line of said static memorycell.
 2. A semiconductor integrated circuit according to claim 1 ,further comprising a plurality of said static memory cells; wherein thepower supplying nodes of said static memory cells are commonly connectedto said switch.
 3. A semiconductor integrated circuit according to claim1 , further comprising a voltage converter having an input for receivinga second supply voltage, and an output having said first supply voltage,wherein the maximum voltage of said data line is determined by saidsecond supply voltage, and wherein said first supply voltage is higherthan said second supply voltage.
 4. A semiconductor integrated circuitaccording to claim 3 , wherein said semiconductor integrated circuit isoperated by a supply voltage which is lower than the threshold voltageof storage MOS transistors in said static memory cell.
 5. Asemiconductor integrated circuit according to claim 4 , wherein the gateinsulators of the MOS transistor forming said switch and of said staticmemory cell MOS transistors are thicker than the gate insulator of theMOS transistor of a peripheral circuit.
 6. A semiconductor integratedcircuit according to claim 1 , wherein the threshold voltage of atransfer MOS transistor in said static memory cell is lower than thethreshold voltage of a MOS transistor forming a data storage cell ofsaid static memory cell.
 7. A semiconductor integrated circuit accordingto claim 1 , further comprising means for controlling said switch on andoff in synchronism with the activation timing of a word line of saidstatic memory cell.
 8. A semiconductor integrated circuit according toclaim 1 , further comprising voltage level control means mounted on apower supplying line shared among a plurality of said static memorycells for supplying said first supply voltage.
 9. A semiconductorintegrated circuit, comprising: a static memory cell; a word lineconnected to said static memory cell; a data line connected to saidstatic memory cell; means for receiving power from a power source andfor generating a first power supply voltage for said static memory cell,said first power supply voltage having a first voltage level; and aswitch connecting a first power supply node of said static memory celland said first power supply voltage; wherein said switch is off whensaid word line is activated.
 10. A semiconductor integrated circuitaccording to claim 9 , further comprising: means for receiving powerfrom a power source and for generating a second voltage level which isone-half said first voltage level; wherein a second power supply node ofsaid static memory cell is connected to a reference voltage level;wherein said data line is driven to said second voltage level when saidstatic memory cell is inactivated; and wherein said word line is drivento take one of said reference voltage level and said second voltagelevel.
 11. A semiconductor integrated circuit according to claim 9 ,further comprising: means for receiving power from a power source andfor generating a second voltage level which is higher than thesensitivity voltage of said static memory cell; wherein a second powersupply node of said static memory cell is connected to a referencevoltage level; wherein said data line is driven to said second voltagelevel when said static memory cell is inactivated; and wherein said wordline is driven to take one of said reference voltage level and saidfirst voltage level.
 12. A semiconductor integrated circuit according toclaim 9 , further comprising: means for receiving power from a powersource and for generating a second voltage level which is one-half ofsaid first voltage level; and means for generating, from said secondvoltage level, a third voltage level which is smaller than said secondvoltage level by the sensitivity voltage of said static memory cell;wherein a second power supply node of said static memory cell is drivento a reference voltage level when said word line is inactivated, and tosaid third voltage level when said word line is activated; wherein saiddata line is driven to said second voltage level when said static memorycell is inactivated; and wherein said word line is driven to take one ofsaid reference voltage level and said first voltage level.
 13. Asemiconductor integrated circuit according to claim 9 , wherein a secondpower supply node of said static memory cell is connected to a referencevoltage level; wherein said data line is driven to said first voltagelevel when said static memory cell is inactivated; and wherein said wordline is driven to take one of said reference voltage level and saidfirst voltage level.
 14. A semiconductor integrated circuit according toclaim 9 , wherein said static memory cell includes first and second MOSinverters, one of said inverters having an output connected to the inputof the other of said inverters; a first MOS transistor, one end of saidfirst MOS transistor being connected to the input of said firstinverter; and a second MOS transistor, one end of said second MOStransistor being connected to the output of said first inverter; andwherein said first and second MOS transistors each have a lowerthreshold voltage than those of the MOS transistors contained in saidfirst and second inverters.
 15. A semiconductor integrated circuitaccording to claim 14 , wherein a second power supply node of saidstatic memory cell is connected to a reference voltage level, saidsemiconductor integrated circuit further comprising means for receivingpower from a power source and for generating a second voltage levelwhich is lower than said reference voltage level; wherein said first andsecond inverters are connected to said reference voltage level at powersupply nodes thereof; wherein said data line is driven to said firstvoltage level when said static memory cell is inactivated; and whereinsaid word line is driven to take one of said second voltage level andsaid first voltage level.
 16. A semiconductor integrated circuitaccording to claim 9 , wherein said switch is a MOS transistor having afirst-conduction-type well; and wherein the first-conduction-type wellof said switch and a first conduction type well forming a MOS transistorof said static memory cell are connected to said first voltage level.17. A semiconductor integrated circuit which is driven by a power sourcegenerating a voltage between a reference and a first voltage level,comprising: a static memory cell; a word line connected to said staticmemory cell; a data line connected to said static memory cell; a voltageconverter for generating a second voltage level which is higher thansaid first voltage level; and a switch connected to a higher powersupplying node of said static memory cell and said second voltage level,wherein said switch is turned off when said word line is activated. 18.A semiconductor integrated circuit according to claim 17 , furthercomprising: a second voltage converter to generate a third voltage levelwhich is substantially a half of said first voltage level, wherein alower power supplying node of said static memory cell is connected tosaid reference voltage level, wherein said data line is driven to saidthird voltage level when said static memory cell is inactivated, andwherein said word line is driven to said reference voltage level or saidsecond voltage level.
 19. A semiconductor integrated circuit accordingto claim 17 , further comprising: a second voltage converter to generatea third voltage level which is higher than said reference voltage levelby the sensitivity voltage of said static memory cell, wherein a lowerpower supplying node of said static memory cell is connected to saidreference voltage level, wherein said data line is driven to said thirdvoltage level when said static memory cell is inactivated, and whereinsaid word line is driven to said reference voltage level or said firstvoltage level.
 20. A semiconductor integrated circuit according to claim17 , further comprising: a second voltage converter to generate a thirdvoltage level which is substantially a half of said first voltage level;and a third voltage converter to generate a fourth voltage level whichis smaller than said third voltage level by the sensitivity voltage ofsaid static memory cell, wherein a lower power supplying node of saidstatic memory cell is driven to said reference voltage level when saidword line is inactivated, and to said fourth voltage level when saidword line is activated, wherein said data line is driven to said thirdvoltage level when said static memory cell is inactivated, and whereinsaid word line is driven to said reference voltage level or said firstvoltage level.
 21. A semiconductor integrated circuit according to claim17 , wherein a lower power supplying node of said static memory cell isconnected to said reference voltage level, wherein said data line isdriven to said first voltage level when said static memory cell isinactivated, and wherein said word line is driven to said referencevoltage level or said first voltage level.
 22. A semiconductorintegrated circuit according to claim 17 , wherein said static memorycell includes: first and second inverters each of which has an outputconnected to the input of the other; a first MOS transistor, one end ofwhich is connected to the input of said first inverter; and a second MOStransistor, one end of which is connected to the output of said firstinverter, and wherein said first and second MOS transistors each have athreshold voltage which is smaller than that of the MOS transistorscontained in said first and second inverters.
 23. A semiconductorintegrated circuit according to claim 22 , further comprising: a secondvoltage converter to generate a third voltage level which is smallerthan said reference voltage level, wherein the lower power supplyingnodes of said first and second inverters are connected to said referencevoltage level, wherein said data line is driven to said first voltagelevel when said static memory cell is inactivated, and wherein said wordline is driven to said third voltage level or said first voltage level.24. A semiconductor integrated circuit according to claim 17 , whereinsaid switch is a MOS transistor, wherein a first well of a firstconduction type forms the MOS transistor of said switch and a secondwell of said first conduction type forms the MOS transistor of saidstatic memory cell; and wherein said first and second wells areconnected to said second voltage level.
 25. A semiconductor integratedcircuit according to claim 24 , wherein the gate insulators of the MOStransistors of said switch and said static memory cell are thicker thanthat of a MOS transistor of a peripheral circuit.
 26. A semiconductorintegrated circuit which is driven by a power source generating avoltage between a reference and a first voltage level, comprising: aplurality of memory arrays; a voltage converter to generate a secondvoltage level which is higher than said first voltage level; and aglobal word line extending over said plurality of memory arrays, whereineach of said memory arrays further includes: a plurality of staticmemory cells arranged in a matrix configuration in first and seconddirections intersecting substantially at a right angle; a sub powersupplying line extending in said first direction and connected to higherpower supplying nodes of said plurality of static memory cells in saidfirst direction; a switch connected between said sub power supplyingline and said second voltage level; a word line extending in said firstdirection and connected to said static memory cells in said firstdirection, where said word line is activated so as to correspond to saidglobal word line; and a data line extending in said second direction andconnected to said static memory cells in said second direction, andwherein said switch is turned off when said word line is activated. 27.A semiconductor integrated circuit according to claim 26 , furthercomprising: a second voltage converter to generate a third voltage levelwhich is substantially a half of said first voltage level, wherein alower power supplying node of said static memory cell is connected tosaid reference voltage level, and wherein said data line is driven tosaid third voltage when said static memory cells are inactivated, andwherein said word line is driven to said reference voltage level or saidsecond voltage level.
 28. A semiconductor integrated circuit accordingto claim 26 , further comprising: a second voltage converter to generatea third voltage level which is higher than the sensitivity voltage ofsaid static memory cell, wherein a lower power supplying node of saidstatic memory cell is connected to said reference voltage level, whereinsaid data line is driven to said third voltage level when said staticmemory cells are inactivated, and wherein said word line is driven tosaid reference voltage level or said first voltage level.
 29. Asemiconductor integrated circuit according to claim 26 , furthercomprising: a second voltage converter to generate a third voltage levelwhich is substantially a half of said first voltage level; and a thirdvoltage converter to generate a fourth voltage level which is smallerthan said third voltage level by the sensitivity voltage of said staticmemory cell, wherein a lower power supplying node of said static memorycell is driven to said reference voltage level when said word line isinactivated, and to said fourth voltage level when said word line isactivated, wherein said data line is driven to said third voltage levelwhen said static memory cells are inactivated, and wherein said wordline is driven to said reference voltage level or said first voltagelevel.
 30. A semiconductor integrated circuit according to claim 26 ,wherein a lower power supplying node of said static memory cells isconnected to said reference voltage level, wherein said data line isdriven to said first voltage level when said static memory cells areinactivated, and wherein said word line is driven to said referencevoltage level or said first voltage level.
 31. A semiconductorintegrated circuit according to claim 26 , wherein each of said staticmemory cells includes: first and second inverters each of which has anoutput connected to the input of the other; a first MOS transistor, oneend of which is connected to the input of said first inverter; and asecond MOS transistor, one end of which is connected to the output ofsaid first inverter, and wherein said first and second MOS transistorseach have a threshold voltage which is smaller than that of the MOStransistors contained in said first and second inverters.
 32. Asemiconductor integrated circuit according to claim 31 , furthercomprising: a second voltage converter to generate a third voltage levelwhich is smaller than said reference voltage level, wherein the lowerpower supplying nodes of said first and second inverters are connectedto said reference voltage level, wherein said data line is driven tosaid first voltage level when said static memory cells are inactivated,and wherein said word line is driven to said third voltage level or saidfirst voltage level.
 33. A semiconductor integrated circuit according toclaim 26 , wherein said switch is a MOS transistor, wherein a first wellof a first conduction type forms the MOS transistor of said switch and asecond well of said first conduction type forms the MOS transistor ofone of said static memory cells, and wherein said first and second wellsare connected to said second voltage level.
 34. A semiconductorintegrated circuit according to claim 33 , wherein the gate insulatorsof the MOS transistors of said switch and said static memory cells arethicker than that of a transistor of a peripheral circuit.
 35. Asemiconductor integrated circuit which is driven by a power sourcegenerating a voltage between a reference and a first voltage level,comprising: a static memory cell including: first and second inverterseach of which has an output connected to the input of the other; a firstMOS transistor, one end of which is connected to the input of said firstinverter; and a second MOS transistor, one end of which is connected tothe output of said first inverter; a word line connected to the gates ofsaid first and second MOS transistors; a pair of complementary datalines connected to the individual other ends of said first and secondMOS transistors; a voltage converter to generate a second voltage levelwhich is higher than said first voltage level; and a switch connectedbetween the higher power supplying nodes of said first and secondinverters and said second voltage level, wherein said first and secondMOS transistors have a threshold voltage that is lower than that of theMOS transistors contained in said first and second inverters.
 36. Asemiconductor integrated circuit according to claim 35 , furthercomprising: a second voltage converter to generate a third voltage levelwhich is lower than said reference voltage level, wherein the lowerpower supplying nodes of said first and second inverters are connectedto said reference voltage level, wherein said data line is driven tosaid first voltage level when said static memory cell is inactivated,and wherein said word line is driven to said third voltage level or saidfirst voltage level.
 37. A semiconductor integrated circuit according toclaim 36 , wherein said switch is a MOS transistor, wherein a first wellof a first conduction type forms the MOS transistor of said switch and asecond well of said first conduction type forms the MOS transistor ofsaid static memory cell, and wherein said first and second wells areconnected to said first voltage level.
 38. A semiconductor integratedcircuit according to claim 37 , wherein the gate insulators of the MOStransistors of said switch and said static memory cell are thicker thanthat of a transistor of a peripheral circuit.
 39. A semiconductorintegrated circuit which is driven by a power source generating avoltage between a reference and a first voltage level, comprising: astatic memory cell including: first and second inverters each of whichhas an output connected to the input of the other; a first MOStransistor, one end of which is connected to the input of said firstinverter; and a second MOS transistor, one end of which is connected tothe output of said first inverter; a word line connected to the gates ofsaid first and second MOS transistors; a pair of complementary datalines connected to the individual other ends of said first and secondMOS transistors; a voltage converter to generate a second voltage levelwhich is higher than said first voltage level; and a switch connectedbetween the higher power supplying nodes of said first and secondinverters and said second voltage level, wherein the difference betweensaid reference voltage level and said first voltage level is smallerthan the threshold voltage of the MOS transistors contained in saidfirst and second inverters.
 40. A semiconductor integrated circuitaccording to claim 39 , wherein said first and second MOS transistorshave a threshold voltage that is lower than that of the MOS transistorscontained in said first and second inverters.
 41. A semiconductorintegrated circuit according to claim 40 , further comprising: a secondvoltage converter to generate from a third voltage level which is lowerthan said reference voltage level, wherein lower power supplying nodesof said first and second inverters are connected to said referencevoltage level, wherein said data line is driven to said first voltagelevel when said static memory cell is inactivated, and wherein said wordline is driven to said third voltage level or said first voltage level.42. A semiconductor integrated circuit according to claim 41 , whereinsaid switch is a MOS transistor, wherein a first well of a firstconduction type forms the MOS transistor of said switch and a secondwell of said first conduction type forms the MOS transistor of saidstatic memory cell, and wherein said first and second wells areconnected to said first voltage level.
 43. A semiconductor integratedcircuit according to claim 42 , wherein the gate insulator of the MOStransistors of said switch and said static memory cell is thicker thanthat of a transistor of a peripheral circuit.
 44. A semiconductorintegrated circuit, comprising: a static memory cell; a word lineconnected to said static memory cell; a data line connected to saidstatic memory cell; a first voltage converter having an input connectedto a power source, and an output having a first voltage level; and aswitch connected between said first voltage converter output and a firstpower supply node of said static memory cell; wherein said switch is offwhen said word line is activated.
 45. A semiconductor integrated circuitaccording to claim 44 , further comprising: a second voltage converterhaving an input connected to a power source, and an output having asecond voltage level which is one-half said first voltage level; whereina second power supply node of said static memory cell is connected to areference voltage level that is lower than said first voltage level;wherein said data line is driven to said second voltage level when saidstatic memory cell is inactivated; and wherein said word line is drivento one of said reference voltage level and said second voltage level.46. A semiconductor integrated circuit according to claim 44 , furthercomprising: a second voltage converter having an input connected to apower source, and an output having a second voltage level that is higherthan the sensitivity voltage of said static memory cell; wherein asecond power supply node of said static memory cell is connected to areference voltage level that is lower than-said first voltage level;wherein said data line is driven to said second voltage level when saidstatic memory cell is inactivated; and wherein said word line is drivento one of said reference voltage level and said first voltage level. 47.A semiconductor integrated circuit according to claim 44 , furthercomprising: a second voltage converter having an input connected to apower supply, and an output having a second voltage level that isone-half of said first voltage level; and a third voltage converterhaving an input connected to a power supply, and an output having athird voltage level that is smaller than said second voltage level bythe sensitivity voltage of said static memory cell; wherein a secondpower supply node of said static memory cell is driven to a referencevoltage level that is smaller than said first voltage level when saidword line is inactivated, and to said third voltage level when said wordline is activated; wherein said data line is driven to said secondvoltage level when said static memory cell is inactivated; and whereinsaid word line is driven to one of said reference voltage level and saidfirst voltage level.
 48. A semiconductor integrated circuit according toclaim 44 , wherein a second power supply node of said static memory cellis connected to a reference voltage level that is smaller than saidfirst voltage level; wherein said data line is driven to said firstvoltage level when said static memory cell is inactivated; and whereinsaid word line is driven to one of said reference voltage level and saidfirst voltage level.
 49. A semiconductor integrated circuit according toclaim 44 , wherein said static memory cell includes first and second MOSinverters, one of said inverters having an output connected to the inputof the other of said inverters; a first MOS transistor, one end of saidfirst MOS transistor being connected to the input of said firstinverter; and a second MOS transistor, one end of said second MOStransistor being connected to the output of said first inverter; andwherein said first and second MOS transistors each have a lowerthreshold voltage than those of the MOS transistors contained in saidfirst and second inverters.
 50. A semiconductor integrated circuitaccording to claim 49 , wherein a second power supply node of saidstatic memory cell is connected to a reference voltage level that issmaller than said first voltage level, said semiconductor integratedcircuit further comprising: means for receiving power from a powersource and for generating a second voltage level which is lower thansaid reference voltage level; wherein said first and second invertersare connected to said reference voltage level at power supply nodesthereof; wherein said data line is driven to said first voltage levelwhen said static memory cell is inactivated; and wherein said word lineis driven to take one of said second voltage level and said firstvoltage level.